The present invention relates to a super integration circuit device having a plurality of IC-chip equivalent regions, each normally available as a one-chip IC device on a single semiconductor substrate.
The expression "IC-chip equivalent region" is used in the specification to describe an integrated circuit pattern which was initially developed to be manufactured as a single integrated circuit on a chip, but which is now formed as one part of a large scale integrated (LSI) device located on a single semiconductor substrate. This is explained in the specification and the terminology is used consistently throughout the specification to describe such a pattern. The "IC-chip equivalent region" is also called a super macro-cell (abbreviated as SMC hereinafter) in this specification.
Along with the recent development of LSI technology, the number of transistors formed on a single semiconductor chip has remarkably increased. Strong demand has arisen for providing one chip consisting of a plurality of LSIs arranged as an electronic equipment, so as to reduce the cost of the electronic equipment and improve its reliability. There has been proposed an effective technology to produce one chip integration including a plurality of large function blocks corresponding to LSI parts (U.S. Ser. No. 613,302). The assignee of that application is also the assignee of the present application. A typical example is illustrated in FIG. 1. Referring to FIG. 1, on a semiconductor substrate or chip I, IC-chip equivalent regions or SMCs A and B are formed together. These regions A and B have been evaluated as discrete IC chips. Since a plurality of SMCs are integrated on the single semiconductor chip I, which serves as a large scale integrated (LSI) circuit, it is called a super integration (abbreviated as SI hereinafter). Bonding pads b1, b2, . . . and c1, c2, . . . are formed at periphery portions of IC-chips which are now used as IC-chip equivalent regions A and B, respectively; and bonding pads d1, d2, . . . are formed at periphery portion of chip I. The evaluated regions A and B are separated by appropriate space e, on the semiconductor chip I. Space e corresponds to a routing region to which interconnections f1, f2, . . . between regions A and B are allocated. Another routing region is formed near the peripheral portion of chip I, and is used for providing interconnections g1, g2, g3, g4, . . . to bonding pads d1, d2, d3, . . . These pads d1, d2, . . . are used as lead terminals of one-chip SI, so as to connect the lead terminals d1, d2, . . . to an external circuit.
A conventional test technique (B. Koehler, "Designing a Microcontroller "Supercell" for Testability", VLSI DESIGN, Oct. 1983, pp. 44-46) is proposed to test a one-chip VLSI obtained by integrating SMCs (IC-chip equivalent regions). According to this technique, an SMC being tested is set completely independent of other SMCs using an I/O terminal, and is directly accessed from an external terminal during the test. The SMCs shown in FIG. 2 can be individually tested. FIG. 2 shows a circuit constructed by the inventors by using the concept of the above-mentioned conventional test technique. In the figure, portions corresponding to those of FIG. 1 are denoted by the same or corresponding reference numerals. Referring to FIG. 2, reference numeral A denotes a developed and evaluated SMC exemplified by a microprocessor. Reference numeral B denotes a circuit portion additionally developed to be used in standard cells or the like and referred to as a random section. Random section B also functions as an SMC. Reference numeral 1 denotes a bidirectional address bus; 2, a bidirectional data bus; 3 to 5, unidirectional control buses; 6, an output bus; and 7, an input bus.
SMC A includes address bus buffer 11, data bus buffer 12, control bus buffer 13, and an ALU (not shown). Buffer 13 consists of input and output sections. Section B comprises address bus buffer 21, data bus buffer 22, control bus buffer 23, output buffer 24, input buffer 25, and other circuits (not shown). Buffer 11 is a 3-state buffer connected to bus 1. Buffer 12 is an input/output buffer connected to bus 2. An output from buffer 23 in section B is supplied to the input section of buffer 13 through bus 5. An external direct signal is supplied to the input section in buffer 13 through bus 3. Buffer 13 directly outputs a signal onto bus 4. A signal from buffer 13 is also supplied to the input section of buffer 23 in section B through bus 4. An external signal is supplied to buffer 25 through wirings or bus g4. Buffer 24 directly outputs a signal onto wirings or bus g3. Buffer 21 consists of input and output sections. A signal from bus 1 is supplied to the input section in buffer 21. The output section of buffer 21 is a 3-state buffer. An output from this 3-state buffer is sent onto bus 1. Bus buffer 22 comprises an input/output buffer connected to bus 2. A test signal is supplied to both sections A and B.
The arrangement in FIG. 2 is designed as follows: when a test signal is supplied to sections A and B, (I) an output from buffer 21 is set inactive in response to the test signal; (II) buffer 22 is set inactive in response to the test signal; and (III) if signals from the output section in buffer 13 include one which is not directly output, the indirect output is conducted to buffer 24 in response to the test signal so that the indirect output can be output from the buffer 24. At the same time, the signal input to the input section in buffer 13 is directly supplied thereto from external input buffer 25 in response to the test signal. In this case, when the test signal is set active, SMC A is completely disconnected from section B. All buffers in SMC A can be externally accessed in a direct manner. More specifically, an existing test program for SMCs can be used without modifications.
However, the signal input from section B to the input section in buffer 13 in SMC A through bus 5 cannot be directly monitored at an external tester. Therefore, a means for detecting waveforms and propagation delay time of the signals appearing on bus 5 is limited to simulation. The SMC test program, simulation process data, and the simulation program are not released to general users. It is, therefore, very difficult for the users to evaluate either individual SMCs or the entire LSI made of SMCs.